Circuit Analysis Using a Two-Port Transformation

Quote of the Day

The power of instruction is seldom of much efficacy except in those happy dispositions where it is almost superfluous.

— Gibbon. I think this quote is a bit harsh, but not off too much. I recently have been taking some online classes where I work problems and can ask the instructor questions if I have issues. In this case, there really is no instruction – I am just reading the book and getting the opportunity to ask an expert questions. It works.


Introduction

Figure 1: Simple Voltage Regulator with Current Limit.

Figure 1: Simple Voltage Regulator with Current Limit.

I was doing some reading on the Planet Analog web site when I encountered an interesting blog post by Dennis Feucht on a simple BJT-based voltage regulator with an output current limit.

I thought Dennis' post was good because it (1) provided a very clean demonstration of the use of Thevenin and beta transform equivalent circuits for analysis, and (2) it also provide me a good demonstration for how to use a computer-algebra system to help you design a circuit.

I am always looking for good Mathcad reference applications for my staff. In this post, I illustrate the the basic circuit transformation and then use Mathcad to determine component values and predict circuit performance. I also simulate the circuit using LTSpice (Appendix A).

I should point out that even though this circuit is simple, the algebra can get overwhelming. The gods of electronics work by simple rules, but they have no fear of algebra.

Background

Motivation

I am always looking for simple power conversion circuits to use for my home projects. I like to see current-limited power sources for safety reasons. The performance of this circuit is not great, but there are ways to improve it – I will cover these later.

General Operation

This circuit really operates in two modes (see Appendix A for simulation details):

  • Q1 Saturated

    When not limiting the output current, Q1 is saturated. As such, Q1 dissipates relatively little power.

  • Q1 Active

    When limiting the output current, Q1 is in the active region and is dissipating significant power.

Analysis

Simple Model

Figure 2 shows the circuit of Figure 1 with a simple DC PNP transistor model and the base circuit transformed to a Thevenin equivalent.

Figure M: Equivalent Circuit. Figure M: Equivalent Circuit.

Figure 2: Equivalent Circuit.

Circuit with Beta Transformation

Figure 3 shows the circuit of Figure 2 using a beta transformation.

 Figure M: Equivalent Circuit with Impedance Transformation.


Figure 3: Equivalent Circuit with Impedance Transformation.

Derivations

Derivation of Formulas for the RI and RB Values

Figure 4 shows how to analyze the circuit in Figure 3 for RE and RB. Note how I grabbed an intermediate term to determine the constraint for a positive RE value.

Figure M: Derivation of RI and RB.

Figure 4: Derivation of RI and RB.

Derivation of Constraint on RE

Figure 5 shows how to derive the constraint on RB that ensures positive RE.

Figure M: Derive Constraint on RB.

Figure 5: Derive Constraint on RB.

Derivation of RE Equation

Figure 6 shows to derive the expression for RE. I start with the expression shown in Figure 4 with the bubble numbered 1.

Figure 6: Derivation of RE.

Figure 6: Derivation of RE.

Example

Figure 7 shows the example worked on the blog post.

Figure M: Example from the Blog Post.

Figure 7: Example from the Blog Post.

Conclusion

This was a good illustration of the capabilities of a computer algebra system for a simple electronic circuit. This current-limited voltage source served that purpose well.

Appendix A: LTSpice Simulation

I captured the circuit in LTSpice (Figure 8).

Figure 8: LTSpice Version of This Circuit.

Figure 8: LTSpice Version of This Circuit.

Figure 9 shows my simulation result. The values are in the range I would expect for this circuit.

Figure 9: LTSpice Output.

Figure 9: LTSpice Output.

 
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2 Responses to Circuit Analysis Using a Two-Port Transformation

  1. Gene Mirro says:

    In your figure 1, shouldn't R1 be connected to Vs+ ?

     

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